1. Field of the Invention
The present invention relates to a multi-chip package structure, particularly to a multi-chip package structure having a sub-package.
2. Description of the Related Art
The requirement of high density, high performance and precise cost control from, an electronic product speeds up the developments of System On a Chip (SOC) and System In a Package (SIP). The mostly used package technique is Multi-Chip Module (MCM), which integrates the chips having different functions, such as microprocessors, memories, logic elements, optical ICs and capacitors, and replaces the prior art of disposing individual packages on one circuit board.
FIGS. 1 and 2 show the perspective and cross-sectional views of a conventional Multi-Chip Module package structure, respectively. The conventional Multi-Chip Module package structure 10 comprises a first substrate 11, a first package structure 12, a second package structure 13 and a plurality of first solder balls 14.
The first substrate 11 has a top surface 111 and a bottom surface 112. The first solder balls 14 are formed on the bottom surface 112 of the first substrate 11. The first package structure 12 comprises a first chip 121, a plurality of first wires 122 and a first molding compound 123. The first chip 121 is adhered to the top surface 111 of the first substrate 11, and is electrically connected to the first substrate 11 by utilizing the first wires 122. The first molding compound 123 encapsulates the first chip 121, the first wires 122 and part of the top surface 111 of the first substrate 11.
The second package structure 13 comprises a second substrate 131, a second chip 132, a plurality of second wires 133, a second molding compound 134 and a plurality of second solder balls 135. The second substrate 131 has a top surface 1311 and a bottom surface 1312. The second chip 132 is adhered to the top surface 1311 of the second substrate 131, and is electrically connected to the second substrate 131 by utilizing the second wires 133. The second molding compound 134 encapsulates the second chip 132, the second wires 133 and part of the top surface 1311 of the second substrate 131. The second solder balls 135 are formed on the bottom surface 1312 of the second substrate 131. The second package structure 13 is attached to the top surface 111 of the first substrate 11 by surface mounting that utilizes the second solder balls 135 after the second package structure 13 itself has been packaged.
In the conventional Multi-Chip Module package structure 10, the first chip 121 is a microprocessor chip, and the second chip 132 is a memory chip. Because different memory chips have different sizes and different amounts of I/O pins, it is necessary to redesign signal-transmitting path when the microprocessor chip is integrated with different memory chips, which increases the manufacture cost and extends the research time. Additionally, in the conventional Multi-Chip Module package structure 10, the first package structure 12 and the second package structure 13 are disposed in parallel relationship, which occupies a relative large area.
Consequently, there is an existing need for a novel and improved multi-chip package structure to solve the above-mentioned problem.